As semiconductor wafers progress to higher density chips with shrinking geometries, the materials and processes used in wafer fabrication are changing. At the same time, some chips have literally tens of billions of electrical connections between the various metal layers and silicon devices. Electrical performance is improved though concurrent scaling of device features. An indicator of chip performance is the speed at which signals are transmitted. Decreased geometries translate into reduced interconnect linewidths which in turn lead to increased resistance (“R”). Furthermore, reduced spacing between conductor lines creates more parasitic line capacitance (“C”). One result is an increase in RC signal delay. The line capacitance is directly proportional to the k-value of the dielectric. Therefore, new materials are needed to compensate for these phenomena and still maintain electrical performance. New metal conductor materials, such as copper (“Cu”), and new low-k insulating dielectric materials, such as silicon low-k (“SiLK”), have been introduced. Copper can provide reduced resistivity over the traditionally used aluminum (“Al”). Low-k materials can provide reduced line capacitance over the traditionally used silicon dioxide (“SiO2”).
Multiple conductive and insulating layers are required to enable the interconnection and isolation of devices on different layers. The interlayer dielectric (“ILD”) serves as an insulator material between each metal layer or between a first metal layer and the wafer. ILDs can be made of a low-k insulating material, such as SiLK. ILDs have many small vias, which are openings in the ILD that provide an electrical pathway from one metal layer to an adjacent metal layer. Metal layers can be made of copper. Vias are filled with a conductive metal, traditionally tungsten and more recently copper.
In Cu/low-k interconnect architectures, the connecting vias between metal layers are subject to significant mechanical stresses that can result in, for example, via resistance increases. This is particularly true when Cu lines are embedded in a “soft” low-k dielectric, such as SiLK, and the final, or any intermediate, Cu metal layer on top is then covered or embedded in a “hard” dielectric layer, such as oxide or fluorosilicate glass (“FSG”). Under stress, cracks can form in the “hard” dielectric. These cracks can open the dielectric to environmental contamination, such as oxygen and moisture diffusion.
It is therefore desirable to provide a solution that can reduce the thermo-mechanical stress on vias and reduce cracking in the hard dielectric. Exemplary embodiments of the present invention can provide this by introducing a stress-relief layer between the vias and the hard dielectric layer. Such a stress-relief layer can, in some embodiments, include a “soft” dielectric material, such as a low-k insulating material.